1. Field of the Invention
The present invention is directed generally to memory cells and, more particularly, to dynamic random access memory cells fabricated utilizing ultra-large scale integration techniques.
2. Description of the Background
Prior art dynamic random access memories (DRAMs) utilize a variety of different circuit constructions. However, all DRAMs utilize a capacitor to store a charge representative of the information to be stored. For example, the capacitor may store a positive charge representative of a first logic level (a logic "one") with the absence of that positive charge interpreted as a second logic level (a logic "zero"). The capacitor can be accessed through a single transistor for both reading the charge stored on the capacitor or storing a charge on the capacitor. Consequently, DRAMs can operate at the very high clock speeds required by modern processors.
For each bit of information to be stored, a typical DRAM must provide a relatively large 25 ff capacitor. Although DRAM designers have been very clever in devising circuit architectures in which the capacitor is fabricated in a trench or stacked on top of other components so that the capacitor takes up less planer space, scaling the capacitor itself to smaller sizes represents a major challenge. Furthermore, the fabrication steps needed for such circuit architectures complicate the ultra-large scale integration processes used to fabricate such components.
One type of memory device that avoids the use of capacitors for storing charge is the flash memory. A flash memory relies upon a floating gate of a transistor to represent the state of each memory cell. For example, if the floating gate stores a charge such that upon the application of a voltage to the gate terminal the transistor is rendered conductive, that current may represent a first state. If the floating gate does not store any charge such that upon the application of a voltage to the transistor's gate terminal no current flows, the absence of such current may represent a second state. By using the capacitance of the floating gate to store the charge instead of a typical DRAM cell capacitor, flash memories can have a higher density and therefor a smaller size than similarly sized DRAMs. Flash memories are well know in the art as shown, for example, by U.S. Pat. No. 5,600,593 entitled Apparatus And Method For Reducing Erased Threshold Voltage Distribution In Flash Memory Arrays.
The floating gate in a flash memory is essential for the memory's non-volatile operation. However, because the gate is isolated to enable it to store charge and float, it is difficult to write to such devices. Essentially, the charge to be stored by the floating gate must be forced to tunnel through nonconductive dielectric material. As a result, flash memories cannot compete with DRAMs and static random access memories (SRAMs) in terms of speed performance.
A need exists for a memory device which does not rely on a large capacitor for storing charge while maintaining operating speeds substantially equal to those of state of the art DRAMs.